A condensed look at Section 3 of "SEE Mitigation for FPGAs in Low Earth Orbit" — the effects an SRAM FPGA experiences on orbit, from a routine configuration bit flip to a mission-ending latchup.
In an SRAM FPGA, the most frequent effect is a configuration upset that silently rewires the circuit until it is scrubbed. Latchup is the effect that can end the mission. Everything else sits between those two.
A single radiation strike can land on configuration memory, a user register, a clock or reset net, or a power rail — and each landing spot has its own lifetime and fix. The table below is the full spectrum, from the most common (configuration upsets) to the most severe (destructive burnout in the power chain).
| Effect | What happens | Lasts until | Main mitigations |
|---|---|---|---|
| Configuration SEU | A configuration bit flips, changing a LUT, route or setting. SRAM-configured FPGAs only — flash, SONOS and antifuse cells are immune. | Scrub or reconfiguration | Scrubbing, TMR |
| User-state SEU | A flip-flop, BRAM/URAM, LUTRAM/SRL or DSP register flips. Affects every FPGA type. | Overwritten or reset | ECC, TMR, safe FSMs |
| MCU / MBU | One strike flips several adjacent cells. Grows with process scaling in dense CRAM and BRAM. | As an SEU | Interleaving plus ECC, floorplanned TMR |
| SET | A transient on a combinational, clock or reset net gets latched. The main residual effect in flash and antifuse parts. | Next clock edge, or as an SEU once latched | SET filters, triplicated clocks and resets |
| SEFI | An upset in control logic stalls a block or the whole device — configuration controller, POR, JTAG/ICAP, CPU, DDR controller, transceiver or NoC. | Block reset, reconfiguration or power cycle | Watchdogs, supervisor, recovery ladder |
| Micro-SEFI | One control-cell upset corrupts many bits at once. Observed in 28, 20 and 16 nm SRAM FPGAs. | As an SEU | System-level checks |
| SEL / micro-latchup | A parasitic thyristor turns on; current steps from ~0.1 A to amps in bulk CMOS, often on I/O and auxiliary rails. | Power cycle — may be destructive or leave latent damage | Part selection, current sense plus power cycle |
| SEB / SEGR | Burnout or gate rupture in the power MOSFETs of POL converters and load switches feeding the FPGA. | Permanent | Derating, rad-hard power parts |
Designs typically use under 30% of configuration bits, and the share of upsets that affect operation is often under 10%, typically under 5%. One AMD example design has just 0.49% essential bits — the rate that matters is set by the design, not the die.
16 nm CRAM measured about 28× less sensitive per bit than 28 nm devices, but newer parts pack far more bits — a Versal device carries nearly double the CRAM of a Kintex UltraScale. Device-level rates fall much more slowly than per-bit figures suggest.
Interleaving turns most multi-cell upsets into single-bit errors per ECC word. But in beam tests of triple-modular-redundant designs, every observed TMR failure traced back to an MCU hitting routing shared by two of the three domains.
One recorded event corrupted 1,024 bits across the same bit position in 512 words — enough to make standard error-correction flag every one of those words as uncorrectable at once, even though each word looked like a routine single-bit error.
Commercial 28 nm parts showed 105–125 mA steps that only a power cycle clears. A 16 nm part showed high-current events at every radiation level tested, and one event was destructive with no current limit in place.
Burnout and gate rupture strike the power MOSFETs in point-of-load converters and load switches, not the FPGA itself — but they take the FPGA down just the same, and that failure is permanent.
This is a summary of Section 3, "Single-event effects in FPGAs," from SEE Mitigation for FPGAs in Low Earth Orbit. For the full environment analysis, part-by-part data, mitigation architecture and worked reliability model, read the complete paper (PDF).